1. Field of the Invention
This invention is related to the field of processors and, more particularly, to generating addresses in processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
In the x86 architecture, the generation of addresses can require the addition of up to four values. In order to increase the address size to 64 bits, additional hardware and/or computation time may be necessary to support address generation. While a four input, 64 bit adder may allow 64 bit addresses to be generated in an x86 architecture, such an adder may increase the complexity of the hardware required to perform the address generation. In addition, such an adder may not be able to compute the address fast enough to support increased clock speeds in the processor. It would be desirable to minimize the amount of hardware and computation time needed to generate 64 bit addresses.
The problems outlined above are in large part solved by an apparatus and method that minimize the hardware and computation time needed to generate 64 bit addresses. To generate a 64 bit address, an address generation unit may need to add a 64 bit base value, a 64 bit index value, and a 32 bit displacement value to a 64 bit segment descriptor table address. The address generation unit can include a first adder and a second adder. The first adder can add a displacement to a first portion of the segment descriptor table address to generate an intermediate result. The intermediate result can be concatenated with a second portion of the segment descriptor table address and this concatenated result can be conveyed to the second adder. The second adder can add the concatenated result to a base value and an index value to generate a virtual address.
To insure that the first adder does not generate a carry bit, the segment descriptor table address is required to be aligned on an address boundary and the displacement value is required not to exceed a maximum value. The address boundary can be an integer multiple of a fixed number of bytes and a fault can be generated if the segment descriptor table address is not aligned on this boundary.
In one embodiment, the first adder can comprise a two input, 32 bit adder and the second adder can comprise a three input, 64 bit adder. The first adder may be configured to generate the intermediate result in a first clock cycle and the second adder may be configured to generate the virtual address in a second clock cycle that immediately follows the first clock cycle. In this manner, the apparatus and method described herein may advantageously permit 64 bit addresses to be generated while minimizing the hardware needed to do so and permitting increased clock speeds in a processor.